/* Date Stamp: 9/4/2013 */

#ifndef IIO_DFX_IOSF_h
#define IIO_DFX_IOSF_h

#include "DataTypes.h"

/* Device and Function specifications:                                        */
/* For BDX_HOST:                                                              */
/* IIO_DFX_IOSF_BDX_DEV 6                                                     */
/* IIO_DFX_IOSF_BDX_FUN 3                                                     */

/* VID_IIO_DFX_IOSF_REG supported on:                                         */
/*       BDX (0x20033000)                                                     */
/* Register default value:              0x8086                                */
#define VID_IIO_DFX_IOSF_REG 0x12032000

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * generated by critter 06_3_0x000
 */
typedef union {
  struct {
    UINT16 vendor_identification_number : 16;
    /* vendor_identification_number - Bits[15:0], RO, default = 16'b1000000010000110 
       The value is assigned by PCI-SIG to Intel.
     */
  } Bits;
  UINT16 Data;
} VID_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* DID_IIO_DFX_IOSF_REG supported on:                                         */
/*       BDX (0x20033002)                                                     */
/* Register default value:              0x6F13                                */
#define DID_IIO_DFX_IOSF_REG 0x12032002

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * generated by critter 06_3_0x002
 */
typedef union {
  struct {
    UINT16 device_identification_number : 16;
    /* device_identification_number - Bits[15:0], RO, default = 16'b0110111100010011 
       Device ID values vary from function to function. Bits 15:8 are equal to 0x6F for 
       the processor. The following list is a breakdown of the function groups. 
       0x6F00 - 0x6F1F : PCI Express and DMI ports
       0x6F20 - 0x6F3F : IO Features (CBDMA, APIC, VT, RAS, Intel TXT)
       0x6F40 - 0x6F5F : Performance Monitors
       0x6F60 - 0x6F7F : DFX
       0x6F80 - 0x6F9F : Intel Quick Path Interface
       0x6FA0 - 0x6FBF : Home Agent/Memory Controller
       0x6FC0 - 0x6FDF : Power Management
       0x6FE0 - 0x6FFF : Cbo/Ring
       
     */
  } Bits;
  UINT16 Data;
} DID_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* PCICMD_IIO_DFX_IOSF_REG supported on:                                      */
/*       BDX (0x20033004)                                                     */
/* Register default value:              0x0000                                */
#define PCICMD_IIO_DFX_IOSF_REG 0x12032004

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * generated by critter 06_3_0x004
 */
typedef union {
  struct {
    UINT16 iose : 1;
    /* iose - Bits[0:0], RO, default = 1'b0 
       1
     */
    UINT16 mse : 1;
    /* mse - Bits[1:1], RO, default = 1'b0 
       1
     */
    UINT16 bme : 1;
    /* bme - Bits[2:2], RO, default = 1'b0 
       1
     */
    UINT16 sce : 1;
    /* sce - Bits[3:3], RO, default = 1'b0 
       1
     */
    UINT16 mwie : 1;
    /* mwie - Bits[4:4], RO, default = 1'b0 
       1
     */
    UINT16 vga_palette_snoop_enable : 1;
    /* vga_palette_snoop_enable - Bits[5:5], RO, default = 1'b0 
       Not applicable to internal devices. Hardwired to 0.
     */
    UINT16 perre : 1;
    /* perre - Bits[6:6], RW, default = 1'b0 
       1
     */
    UINT16 idsel_stepping_wait_cycle_control : 1;
    /* idsel_stepping_wait_cycle_control - Bits[7:7], RO, default = 1'b0 
       Not applicable to internal devices. Hardwired to 0.
     */
    UINT16 serre : 1;
    /* serre - Bits[8:8], RW, default = 1'b0 
       1
     */
    UINT16 fast_back_to_back_enable : 1;
    /* fast_back_to_back_enable - Bits[9:9], RO, default = 1'b0 
       Not applicable to PCI Express and is hardwired to 0
     */
    UINT16 intx_interrupt_disable : 1;
    /* intx_interrupt_disable - Bits[10:10], RO, default = 1'b0 
       1
     */
    UINT16 rsvd : 5;
    /* rsvd - Bits[15:11], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT16 Data;
} PCICMD_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* PCISTS_IIO_DFX_IOSF_REG supported on:                                      */
/*       BDX (0x20033006)                                                     */
/* Register default value:              0x0010                                */
#define PCISTS_IIO_DFX_IOSF_REG 0x12032006

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * generated by critter 06_3_0x006
 */
typedef union {
  struct {
    UINT16 rsvd_0 : 3;
    /* rsvd_0 - Bits[2:0], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT16 intxstat : 1;
    /* intxstat - Bits[3:3], RO, default = 1'b0 
       1
     */
    UINT16 capl : 1;
    /* capl - Bits[4:4], RO, default = 1'b1 
       1
     */
    UINT16 pci66mhz_capable : 1;
    /* pci66mhz_capable - Bits[5:5], RO, default = 1'b0 
       Not applicable to PCI Express. Hardwired to 0.
     */
    UINT16 rsvd_6 : 1;
    /* rsvd_6 - Bits[6:6], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT16 fb2b : 1;
    /* fb2b - Bits[7:7], RO, default = 1'b0 
       1
     */
    UINT16 mdpe : 1;
    /* mdpe - Bits[8:8], RO, default = 1'b0 
       1
     */
    UINT16 devselt : 2;
    /* devselt - Bits[10:9], RO, default = 2'b00 
       1
     */
    UINT16 sta : 1;
    /* sta - Bits[11:11], RO, default = 1'b0 
       1
     */
    UINT16 rta : 1;
    /* rta - Bits[12:12], RO, default = 1'b0 
       1
     */
    UINT16 rma : 1;
    /* rma - Bits[13:13], RO, default = 1'b0 
       1
     */
    UINT16 sse : 1;
    /* sse - Bits[14:14], RO, default = 1'b0 
       1
     */
    UINT16 dpe : 1;
    /* dpe - Bits[15:15], RO, default = 1'b0 
       1
     */
  } Bits;
  UINT16 Data;
} PCISTS_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* RID_IIO_DFX_IOSF_REG supported on:                                         */
/*       BDX (0x10033008)                                                     */
/* Register default value:              0x00                                  */
#define RID_IIO_DFX_IOSF_REG 0x12031008

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * "PCIe header Revision ID register"
 */
typedef union {
  struct {
    UINT8 revision_id : 8;
    /* revision_id - Bits[7:0], RO_V, default = 8'b00000000 
       Reflects the Uncore Revision ID after reset.
       Reflects the Compatibility Revision ID after BIOS writes 0x69 to any RID 
       register in the processor uncore. 
       
     */
  } Bits;
  UINT8 Data;
} RID_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* CCR_N0_IIO_DFX_IOSF_REG supported on:                                      */
/*       BDX (0x10033009)                                                     */
/* Register default value:              0x00                                  */
#define CCR_N0_IIO_DFX_IOSF_REG 0x12031009

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * PCIe header ClassCode register
 */
typedef union {
  struct {
    UINT8 register_level_programming_interface : 8;
    /* register_level_programming_interface - Bits[7:0], RO_V, default = 8'b00000000  */
  } Bits;
  UINT8 Data;
} CCR_N0_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* CCR_N1_IIO_DFX_IOSF_REG supported on:                                      */
/*       BDX (0x2003300A)                                                     */
/* Register default value:              0x0880                                */
#define CCR_N1_IIO_DFX_IOSF_REG 0x1203200A

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * PCIe header ClassCode register
 */
typedef union {
  struct {
    UINT16 sub_class : 8;
    /* sub_class - Bits[7:0], RO_V, default = 8'b10000000 
       The value changes dependent upon the dev/func accessed. A table of the values 
       can be found in the Class-code tab of the msgch spread-sheet  
          Most dev-func will return 8'h80 for this field except for the following 
       dev-func0,func1,... combinations. The following exceptions will return 8'h01. 
                 dev-0x0 through 0x7 (return 0x4, d0f0 return 0x0 under default 
       settings) 
       	  dev-0x8 func-2
       	  dev-0x9 func-2
       	  dev-0xA func-2
       	  dev-0xB func-1,2,5,6
       	  dev-0x10 func-1,6
       	  dev-0x12 func-1,5
       	  
     */
    UINT16 base_class : 8;
    /* base_class - Bits[15:8], RO_V, default = 8'b00001000 
       The value changes dependent upon the dev-func accessed. A table of the values 
       can be found in the Class-code tab of the msgch spread-sheet  
          Most dev-func will return 8'h08 for this field except for the following 
       dev-func0,func1,... combinations. The following exceptions will return 8'h11. 
                 dev-0x0 through 0x7 (return 0x6)
       	  dev-0x8 func-2
       	  dev-0x9 func-2
       	  dev-0xA func-2
       	  dev-0xB func-1,2,5,6
       	  dev-0x10 func-1,6
       	  dev-0x12 func-1,5
       	  
     */
  } Bits;
  UINT16 Data;
} CCR_N1_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* CLSR_IIO_DFX_IOSF_REG supported on:                                        */
/*       BDX (0x1003300C)                                                     */
/* Register default value:              0x00                                  */
#define CLSR_IIO_DFX_IOSF_REG 0x1203100C

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * generated by critter 06_3_0x00c
 */
typedef union {
  struct {
    UINT8 cacheline_size : 8;
    /* cacheline_size - Bits[7:0], RW, default = 8'b00000000  */
  } Bits;
  UINT8 Data;
} CLSR_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* PLAT_IIO_DFX_IOSF_REG supported on:                                        */
/*       BDX (0x1003300D)                                                     */
/* Register default value:              0x00                                  */
#define PLAT_IIO_DFX_IOSF_REG 0x1203100D

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * generated by critter 06_3_0x00d
 */
typedef union {
  struct {
    UINT8 primary_latency_timer : 8;
    /* primary_latency_timer - Bits[7:0], RO, default = 8'b00000000 
       Not applicable to PCI-Express. Hardwired to 00h.
     */
  } Bits;
  UINT8 Data;
} PLAT_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* HDR_IIO_DFX_IOSF_REG supported on:                                         */
/*       BDX (0x1003300E)                                                     */
/* Register default value:              0x80                                  */
#define HDR_IIO_DFX_IOSF_REG 0x1203100E

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * generated by critter 06_3_0x00e
 */
typedef union {
  struct {
    UINT8 configuration_layout : 7;
    /* configuration_layout - Bits[6:0], RO, default = 7'b0000000 
       This field identifies the format of the configuration header layout. It is Type 
       0 for all these devices. The default is 00h, indicating a 'endpoint device'. 
     */
    UINT8 multi_function_device : 1;
    /* multi_function_device - Bits[7:7], RO, default = 1'b1 
       This bit defaults to 1b since all these devices are multi-function
     */
  } Bits;
  UINT8 Data;
} HDR_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* BIST_IIO_DFX_IOSF_REG supported on:                                        */
/*       BDX (0x1003300F)                                                     */
/* Register default value:              0x00                                  */
#define BIST_IIO_DFX_IOSF_REG 0x1203100F

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * generated by critter 06_3_0x00f
 */
typedef union {
  struct {
    UINT8 bist_tests : 8;
    /* bist_tests - Bits[7:0], RO, default = 8'b00000000 
       Not supported. Hardwired to 00h
     */
  } Bits;
  UINT8 Data;
} BIST_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* SVID_IIO_DFX_IOSF_REG supported on:                                        */
/*       BDX (0x2003302C)                                                     */
/* Register default value:              0x8086                                */
#define SVID_IIO_DFX_IOSF_REG 0x1203202C

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * generated by critter 06_3_0x02c
 */
typedef union {
  struct {
    UINT16 subsystem_vendor_identification_number : 16;
    /* subsystem_vendor_identification_number - Bits[15:0], RW_O, default = 16'b1000000010000110 
       The default value specifies Intel but can be set to any value once after reset.
     */
  } Bits;
  UINT16 Data;
} SVID_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* SDID_IIO_DFX_IOSF_REG supported on:                                        */
/*       BDX (0x2003302E)                                                     */
/* Register default value:              0x0000                                */
#define SDID_IIO_DFX_IOSF_REG 0x1203202E

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * generated by critter 06_3_0x02e
 */
typedef union {
  struct {
    UINT16 subsystem_device_identification_number : 16;
    /* subsystem_device_identification_number - Bits[15:0], RW_O, default = 16'b0000000000000000 
       Assigned by the subsystem vendor to uniquely identify the subsystem
     */
  } Bits;
  UINT16 Data;
} SDID_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* CAPPTR_IIO_DFX_IOSF_REG supported on:                                      */
/*       BDX (0x10033034)                                                     */
/* Register default value:              0x40                                  */
#define CAPPTR_IIO_DFX_IOSF_REG 0x12031034

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * generated by critter 06_3_0x034
 */
typedef union {
  struct {
    UINT8 capability_pointer : 8;
    /* capability_pointer - Bits[7:0], RO, default = 8'b01000000 
       Points to the first capability structure for the device which is the PCIe 
       capability. 
     */
  } Bits;
  UINT8 Data;
} CAPPTR_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* INTL_IIO_DFX_IOSF_REG supported on:                                        */
/*       BDX (0x1003303C)                                                     */
/* Register default value:              0x00                                  */
#define INTL_IIO_DFX_IOSF_REG 0x1203103C

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * generated by critter 06_3_0x03c
 */
typedef union {
  struct {
    UINT8 interrupt_line : 8;
    /* interrupt_line - Bits[7:0], RO, default = 8'b00000000 
       N/A for these devices
     */
  } Bits;
  UINT8 Data;
} INTL_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* INTPIN_IIO_DFX_IOSF_REG supported on:                                      */
/*       BDX (0x1003303D)                                                     */
/* Register default value:              0x00                                  */
#define INTPIN_IIO_DFX_IOSF_REG 0x1203103D

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * generated by critter 06_3_0x03d
 */
typedef union {
  struct {
    UINT8 interrupt_pin : 8;
    /* interrupt_pin - Bits[7:0], RO, default = 8'b00000000 
       N/A since these devices do not generate any interrupt on their own
     */
  } Bits;
  UINT8 Data;
} INTPIN_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* MINGNT_IIO_DFX_IOSF_REG supported on:                                      */
/*       BDX (0x1003303E)                                                     */
/* Register default value:              0x00                                  */
#define MINGNT_IIO_DFX_IOSF_REG 0x1203103E

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * generated by critter 06_3_0x03e
 */
typedef union {
  struct {
    UINT8 mgv : 8;
    /* mgv - Bits[7:0], RO, default = 8'b00000000 
       The Device does not burst as a PCI compliant master.
     */
  } Bits;
  UINT8 Data;
} MINGNT_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* MAXLAT_IIO_DFX_IOSF_REG supported on:                                      */
/*       BDX (0x1003303F)                                                     */
/* Register default value:              0x00                                  */
#define MAXLAT_IIO_DFX_IOSF_REG 0x1203103F

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * generated by critter 06_3_0x03f
 */
typedef union {
  struct {
    UINT8 mlv : 8;
    /* mlv - Bits[7:0], RO, default = 8'b00000000 
       The Device has no specific requirements for how often it needs to access the PCI 
       bus. 
     */
  } Bits;
  UINT8 Data;
} MAXLAT_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* PXPCAP_IIO_DFX_IOSF_REG supported on:                                      */
/*       BDX (0x40033040)                                                     */
/* Register default value:              0x00920010                            */
#define PXPCAP_IIO_DFX_IOSF_REG 0x12034040

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * generated by critter 06_3_0x040
 */
typedef union {
  struct {
    UINT32 capability_id : 8;
    /* capability_id - Bits[7:0], RO, default = 8'b00010000 
       Provides the PCI Express capability ID assigned by PCI-SIG.
     */
    UINT32 next_ptr : 8;
    /* next_ptr - Bits[15:8], RO, default = 8'b00000000 
       Pointer to the next capability. Set to 0 to indicate there are no more 
       capability structures. 
     */
    UINT32 capability_version : 4;
    /* capability_version - Bits[19:16], RO, default = 4'b0010 
       PCI Express Capability is Compliant with Version 1.0 of the PCI Express Spec.
       
       Note:
       This capability structure is not compliant with Versions beyond 1.0, since they 
       require additional capability registers to be reserved. The only purpose for 
       this capability structure is to make enhanced configuration space available. 
       Minimizing the size of this structure is accomplished by reporting version 1.0 
       compliancy and reporting that this is an integrated root port device. As such, 
       only three Dwords of configuration space are required for this structure. 
     */
    UINT32 device_port_type : 4;
    /* device_port_type - Bits[23:20], RO, default = 4'b1001 
       Device type is Root Complex Integrated Endpoint
     */
    UINT32 slot_implemented : 1;
    /* slot_implemented - Bits[24:24], RO, default = 1'b0 
       N/A for integrated endpoints
     */
    UINT32 interrupt_message_number : 5;
    /* interrupt_message_number - Bits[29:25], RO, default = 5'b00000 
       N/A for this device
     */
    UINT32 rsvd : 2;
    /* rsvd - Bits[31:30], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} PXPCAP_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* DEVCAP_IIO_DFX_IOSF_REG supported on:                                      */
/*       BDX (0x40033044)                                                     */
/* Register default value:              0x00008000                            */
#define DEVCAP_IIO_DFX_IOSF_REG 0x12034044

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * generated by critter 06_3_0x044
 */
typedef union {
  struct {
    UINT32 max_payload_size_supported : 3;
    /* max_payload_size_supported - Bits[2:0], RO, default = 3'b000  */
    UINT32 phantom_functions_supported : 2;
    /* phantom_functions_supported - Bits[4:3], RO, default = 2'b00  */
    UINT32 extended_tag_field_supported : 1;
    /* extended_tag_field_supported - Bits[5:5], RO, default = 1'b0  */
    UINT32 endpoint_l0s_acceptable_latency : 3;
    /* endpoint_l0s_acceptable_latency - Bits[8:6], RO, default = 3'b000  */
    UINT32 endpoint_l1_acceptable_latency : 3;
    /* endpoint_l1_acceptable_latency - Bits[11:9], RO, default = 3'b000  */
    UINT32 attention_button_present : 1;
    /* attention_button_present - Bits[12:12], RO, default = 1'b0  */
    UINT32 attention_indicator_present : 1;
    /* attention_indicator_present - Bits[13:13], RO, default = 1'b0  */
    UINT32 power_indicator_present_on_device : 1;
    /* power_indicator_present_on_device - Bits[14:14], RO, default = 1'b0  */
    UINT32 role_based_error_reporting : 1;
    /* role_based_error_reporting - Bits[15:15], RO, default = 1'b1  */
    UINT32 rsvd_16 : 2;
    /* rsvd_16 - Bits[17:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 captured_slot_power_limit_value : 8;
    /* captured_slot_power_limit_value - Bits[25:18], RO, default = 8'b00000000  */
    UINT32 captured_slot_power_limit_scale : 2;
    /* captured_slot_power_limit_scale - Bits[27:26], RO, default = 2'b00  */
    UINT32 rsvd_28 : 4;
    /* rsvd_28 - Bits[31:28], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} DEVCAP_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* DEVCON_IIO_DFX_IOSF_REG supported on:                                      */
/*       BDX (0x20033048)                                                     */
/* Register default value:              0x0000                                */
#define DEVCON_IIO_DFX_IOSF_REG 0x12032048

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * The PCI Express Device Control register controls PCI Express specific 
 * capabilities parameters associated with the device. 
 */
typedef union {
  struct {
    UINT16 correctable_error_reporting_enable : 1;
    /* correctable_error_reporting_enable - Bits[0:0], RO, default = 1'b0 
       N/A for CB DMA
     */
    UINT16 non_fatal_error_reporting_enable : 1;
    /* non_fatal_error_reporting_enable - Bits[1:1], RO, default = 1'b0 
       N/A for CB DMA
     */
    UINT16 fatal_error_reporting_enable : 1;
    /* fatal_error_reporting_enable - Bits[2:2], RO, default = 1'b0 
       N/A for CB DMA
     */
    UINT16 unsupported_request_reporting_enable : 1;
    /* unsupported_request_reporting_enable - Bits[3:3], RO, default = 1'b0 
       N/A for CB DMA
     */
    UINT16 enable_relaxed_ordering : 1;
    /* enable_relaxed_ordering - Bits[4:4], RO, default = 1'b0 
       For most parts, writes from CB DMA are relaxed ordered, except for DMA 
       completion writes. But the fact that CB DMA writes are relaxed ordered is not 
       very useful except when the writes are also non-snooped. If the writes are 
       snooped, relaxed ordering does not provide any particular advantage based on IIO 
       uArch. But when writes are non-snooped, relaxed ordering is required to get good 
       BW and this bit is expected to be set. If this bit is clear, NS writes will get 
       very poor performance. 
     */
    UINT16 max_payload_size : 3;
    /* max_payload_size - Bits[7:5], RO, default = 3'b000 
       N/A for CB DMA
     */
    UINT16 extended_tag_field_enable : 1;
    /* extended_tag_field_enable - Bits[8:8], RO, default = 1'b0  */
    UINT16 phantom_functions_enable : 1;
    /* phantom_functions_enable - Bits[9:9], RO, default = 1'b0 
       Not applicable to CB DMA since it never uses phantom functions as a requester.
     */
    UINT16 auxiliary_power_management_enable : 1;
    /* auxiliary_power_management_enable - Bits[10:10], RO, default = 1'b0 
       Not applicable to CB DMA
     */
    UINT16 enable_no_snoop : 1;
    /* enable_no_snoop - Bits[11:11], RO, default = 1'b0 
       For CB DMA, when this bit is clear, all DMA transactions must be snooped. When 
       set, DMA transactions to main memory can utilize No Snoop optimization under the 
       guidance of the device driver. 
     */
    UINT16 max_read_request_size : 3;
    /* max_read_request_size - Bits[14:12], RO, default = 3'b000 
       N/A to CB DMA since it does not issue tx on PCIE
     */
    UINT16 rsvd : 1;
    /* rsvd - Bits[15:15], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT16 Data;
} DEVCON_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* DEVSTS_IIO_DFX_IOSF_REG supported on:                                      */
/*       BDX (0x2003304A)                                                     */
/* Register default value:              0x0000                                */
#define DEVSTS_IIO_DFX_IOSF_REG 0x1203204A

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * generated by critter 06_3_0x04a
 */
typedef union {
  struct {
    UINT16 correctable_error_detected : 1;
    /* correctable_error_detected - Bits[0:0], RO, default = 1'b0  */
    UINT16 non_fatal_error_detected : 1;
    /* non_fatal_error_detected - Bits[1:1], RO, default = 1'b0  */
    UINT16 fatal_error_detected : 1;
    /* fatal_error_detected - Bits[2:2], RO, default = 1'b0  */
    UINT16 unsupported_request_detected : 1;
    /* unsupported_request_detected - Bits[3:3], RO, default = 1'b0  */
    UINT16 aux_power_detected : 1;
    /* aux_power_detected - Bits[4:4], RO, default = 1'b0  */
    UINT16 transactions_pending : 1;
    /* transactions_pending - Bits[5:5], RO, default = 1'b0  */
    UINT16 rsvd : 10;
    /* rsvd - Bits[15:6], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT16 Data;
} DEVSTS_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* LNKCAP_IIO_DFX_IOSF_REG supported on:                                      */
/*       BDX (0x4003304C)                                                     */
/* Register default value:              0x003BF400                            */
#define LNKCAP_IIO_DFX_IOSF_REG 0x1203404C

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * generated by critter 06_3_0x04c
 */
typedef union {
  struct {
    UINT32 link_speeds_supported : 4;
    /* link_speeds_supported - Bits[3:0], RO, default = 4'b0000  */
    UINT32 maximum_link_width : 6;
    /* maximum_link_width - Bits[9:4], RO, default = 6'b000000  */
    UINT32 active_state_link_pm_support : 2;
    /* active_state_link_pm_support - Bits[11:10], RO, default = 2'b01  */
    UINT32 l0s_exit_latency : 3;
    /* l0s_exit_latency - Bits[14:12], RO, default = 3'b111  */
    UINT32 l1_exit_latency : 3;
    /* l1_exit_latency - Bits[17:15], RO, default = 3'b111  */
    UINT32 clock_power_management : 1;
    /* clock_power_management - Bits[18:18], RO, default = 1'b0  */
    UINT32 surprise_down_error_reporting_capable : 1;
    /* surprise_down_error_reporting_capable - Bits[19:19], RO, default = 1'b1  */
    UINT32 data_link_layer_link_active : 1;
    /* data_link_layer_link_active - Bits[20:20], RO, default = 1'b1  */
    UINT32 link_bandwidth_notification_capability_a : 1;
    /* link_bandwidth_notification_capability_a - Bits[21:21], RO, default = 1'b1  */
    UINT32 rsvd : 2;
    /* rsvd - Bits[23:22], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 port_number : 8;
    /* port_number - Bits[31:24], RO, default = 8'b00000000  */
  } Bits;
  UINT32 Data;
} LNKCAP_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* LNKSTS_IIO_DFX_IOSF_REG supported on:                                      */
/*       BDX (0x20033052)                                                     */
/* Register default value:              0x1000                                */
#define LNKSTS_IIO_DFX_IOSF_REG 0x12032052

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * generated by critter 06_3_0x052
 */
typedef union {
  struct {
    UINT16 current_link_speed : 4;
    /* current_link_speed - Bits[3:0], RO, default = 4'b0000  */
    UINT16 negotiated_link_width : 6;
    /* negotiated_link_width - Bits[9:4], RO, default = 6'b000000  */
    UINT16 rsvd : 1;
    /* rsvd - Bits[10:10], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT16 link_training : 1;
    /* link_training - Bits[11:11], RO, default = 1'b0  */
    UINT16 slot_clock_configuration : 1;
    /* slot_clock_configuration - Bits[12:12], RO, default = 1'b1  */
    UINT16 data_link_layer_link_active : 1;
    /* data_link_layer_link_active - Bits[13:13], RO, default = 1'b0  */
    UINT16 link_bandwidth_management_status_this : 1;
    /* link_bandwidth_management_status_this - Bits[14:14], RO, default = 1'b0  */
    UINT16 link_autonomous_bandwidth_status_this : 1;
    /* link_autonomous_bandwidth_status_this - Bits[15:15], RO, default = 1'b0  */
  } Bits;
  UINT16 Data;
} LNKSTS_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* LNKCAP2_IIO_DFX_IOSF_REG supported on:                                     */
/*       BDX (0x4003306C)                                                     */
/* Register default value:              0x003BF400                            */
#define LNKCAP2_IIO_DFX_IOSF_REG 0x1203406C

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * generated by critter 06_3_0x06c
 */
typedef union {
  struct {
    UINT32 link_speeds_supported : 4;
    /* link_speeds_supported - Bits[3:0], RO, default = 4'b0000  */
    UINT32 maximum_link_width : 6;
    /* maximum_link_width - Bits[9:4], RO, default = 6'b000000  */
    UINT32 active_state_link_pm_support : 2;
    /* active_state_link_pm_support - Bits[11:10], RO, default = 2'b01  */
    UINT32 l0s_exit_latency : 3;
    /* l0s_exit_latency - Bits[14:12], RO, default = 3'b111  */
    UINT32 l1_exit_latency : 3;
    /* l1_exit_latency - Bits[17:15], RO, default = 3'b111  */
    UINT32 clock_power_management : 1;
    /* clock_power_management - Bits[18:18], RO, default = 1'b0  */
    UINT32 surprise_down_error_reporting_capable : 1;
    /* surprise_down_error_reporting_capable - Bits[19:19], RO, default = 1'b1  */
    UINT32 data_link_layer_link_active : 1;
    /* data_link_layer_link_active - Bits[20:20], RO, default = 1'b1  */
    UINT32 link_bandwidth_notification_capability_a : 1;
    /* link_bandwidth_notification_capability_a - Bits[21:21], RO, default = 1'b1  */
    UINT32 rsvd : 2;
    /* rsvd - Bits[23:22], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 port_number : 8;
    /* port_number - Bits[31:24], RO, default = 8'b00000000  */
  } Bits;
  UINT32 Data;
} LNKCAP2_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* LNKCON2_OLD_IIO_DFX_IOSF_REG supported on:                                 */
/*       BDX (0x20033070)                                                     */
/* Register default value:              0x0000                                */
#define LNKCON2_OLD_IIO_DFX_IOSF_REG 0x12032070

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * generated by critter 06_3_0x070
 */
typedef union {
  struct {
    UINT16 active_state_link_pm_control : 2;
    /* active_state_link_pm_control - Bits[1:0], RO, default = 2'b00  */
    UINT16 rsvd_2 : 1;
    /* rsvd_2 - Bits[2:2], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT16 read_completion_boundary : 1;
    /* read_completion_boundary - Bits[3:3], RO, default = 1'b0  */
    UINT16 link_disable : 1;
    /* link_disable - Bits[4:4], RO, default = 1'b0  */
    UINT16 retrain_link : 1;
    /* retrain_link - Bits[5:5], RO, default = 1'b0  */
    UINT16 common_clock_configuration : 1;
    /* common_clock_configuration - Bits[6:6], RO, default = 1'b0  */
    UINT16 extended_synch : 1;
    /* extended_synch - Bits[7:7], RO, default = 1'b0  */
    UINT16 enable_clock_power_management_na : 1;
    /* enable_clock_power_management_na - Bits[8:8], RO, default = 1'b0  */
    UINT16 hardware_autonomous_width_disable_ioh : 1;
    /* hardware_autonomous_width_disable_ioh - Bits[9:9], RO, default = 1'b0  */
    UINT16 link_bandwidth_management_interrupt_enable : 1;
    /* link_bandwidth_management_interrupt_enable - Bits[10:10], RO, default = 1'b0  */
    UINT16 link_autonomous_bandwidth_interrupt_enable : 1;
    /* link_autonomous_bandwidth_interrupt_enable - Bits[11:11], RO, default = 1'b0  */
    UINT16 rsvd_12 : 4;
    /* rsvd_12 - Bits[15:12], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT16 Data;
} LNKCON2_OLD_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* LNKSTS2_IIO_DFX_IOSF_REG supported on:                                     */
/*       BDX (0x20033072)                                                     */
/* Register default value:              0x1000                                */
#define LNKSTS2_IIO_DFX_IOSF_REG 0x12032072

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * generated by critter 06_3_0x072
 */
typedef union {
  struct {
    UINT16 current_link_speed : 4;
    /* current_link_speed - Bits[3:0], RO, default = 4'b0000  */
    UINT16 negotiated_link_width : 6;
    /* negotiated_link_width - Bits[9:4], RO, default = 6'b000000  */
    UINT16 rsvd : 1;
    /* rsvd - Bits[10:10], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT16 link_training : 1;
    /* link_training - Bits[11:11], RO, default = 1'b0  */
    UINT16 slot_clock_configuration : 1;
    /* slot_clock_configuration - Bits[12:12], RO, default = 1'b1  */
    UINT16 data_link_layer_link_active : 1;
    /* data_link_layer_link_active - Bits[13:13], RO, default = 1'b0  */
    UINT16 link_bandwidth_management_status_this : 1;
    /* link_bandwidth_management_status_this - Bits[14:14], RO, default = 1'b0  */
    UINT16 link_autonomous_bandwidth_status_this : 1;
    /* link_autonomous_bandwidth_status_this - Bits[15:15], RO, default = 1'b0  */
  } Bits;
  UINT16 Data;
} LNKSTS2_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* SLTCAP2_IIO_DFX_IOSF_REG supported on:                                     */
/*       BDX (0x40033074)                                                     */
/* Register default value:              0x00000000                            */
#define SLTCAP2_IIO_DFX_IOSF_REG 0x12034074

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * generated by critter 06_3_0x074
 */
typedef union {
  struct {
    UINT32 attention_button_present : 1;
    /* attention_button_present - Bits[0:0], RO, default = 1'b0  */
    UINT32 power_controller_present : 1;
    /* power_controller_present - Bits[1:1], RO, default = 1'b0  */
    UINT32 mrl_sensor_present : 1;
    /* mrl_sensor_present - Bits[2:2], RO, default = 1'b0  */
    UINT32 attention_indicator_present : 1;
    /* attention_indicator_present - Bits[3:3], RO, default = 1'b0  */
    UINT32 power_indicator_present : 1;
    /* power_indicator_present - Bits[4:4], RO, default = 1'b0  */
    UINT32 hotplug_surprise : 1;
    /* hotplug_surprise - Bits[5:5], RO, default = 1'b0  */
    UINT32 hotplug_capable : 1;
    /* hotplug_capable - Bits[6:6], RO, default = 1'b0  */
    UINT32 slot_power_limit_value : 8;
    /* slot_power_limit_value - Bits[14:7], RO, default = 8'b00000000  */
    UINT32 slot_power_limit_scale : 2;
    /* slot_power_limit_scale - Bits[16:15], RO, default = 2'b00  */
    UINT32 electromechanical_interlock_present : 1;
    /* electromechanical_interlock_present - Bits[17:17], RO, default = 1'b0  */
    UINT32 command_complete_not_capable : 1;
    /* command_complete_not_capable - Bits[18:18], RO, default = 1'b0  */
    UINT32 physical_slot_number : 13;
    /* physical_slot_number - Bits[31:19], RO, default = 13'b0000000000000  */
  } Bits;
  UINT32 Data;
} SLTCAP2_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* SLTSTS2_IIO_DFX_IOSF_REG supported on:                                     */
/*       BDX (0x2003307A)                                                     */
/* Register default value:              0x0000                                */
#define SLTSTS2_IIO_DFX_IOSF_REG 0x1203207A

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * generated by critter 06_3_0x07a
 */
typedef union {
  struct {
    UINT16 attention_button_pressed : 1;
    /* attention_button_pressed - Bits[0:0], RO, default = 1'b0  */
    UINT16 power_fault_detected : 1;
    /* power_fault_detected - Bits[1:1], RO, default = 1'b0  */
    UINT16 mrl_sensor_changed : 1;
    /* mrl_sensor_changed - Bits[2:2], RO, default = 1'b0  */
    UINT16 presence_detect_changed : 1;
    /* presence_detect_changed - Bits[3:3], RO, default = 1'b0  */
    UINT16 command_completed : 1;
    /* command_completed - Bits[4:4], RO, default = 1'b0  */
    UINT16 mrl_sensor_state : 1;
    /* mrl_sensor_state - Bits[5:5], RO, default = 1'b0  */
    UINT16 presence_detect_state : 1;
    /* presence_detect_state - Bits[6:6], RO, default = 1'b0  */
    UINT16 electromechanical_latch_status : 1;
    /* electromechanical_latch_status - Bits[7:7], RO, default = 1'b0  */
    UINT16 data_link_layer_state_changed : 1;
    /* data_link_layer_state_changed - Bits[8:8], RO, default = 1'b0  */
    UINT16 rsvd : 7;
    /* rsvd - Bits[15:9], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT16 Data;
} SLTSTS2_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* GIOINBDC_IIO_DFX_IOSF_REG supported on:                                    */
/*       BDX (0x10033200)                                                     */
/* Register default value:              0x00                                  */
#define GIOINBDC_IIO_DFX_IOSF_REG 0x12031200

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * This register selects which event signal and which header match is active for 
 * in-band debug event messages on this port. 
 */
typedef union {
  struct {
    UINT8 inbmask : 8;
    /* inbmask - Bits[7:0], RWS_L, default = 8'b00000000 
       If a bit field encoding is a logic 1 then that signal may cause an in-band debug 
       event when asserted. 
       
       0000_0000: Disable inband messages
       1xxx_xxxx: GE[5]
       x1xx_xxxx: GE[4]
       xx1x_xxxx: GE[3]
       xxx1_xxxx: GE[2]
       xxxx_1xxx: GE[1]
       xxxx_x1xx: GE[0]
       xxxx_xxx1: Enable inband message w/MRKEN = 1
       
       Notes:
       Locked by RSPLCK
     */
  } Bits;
  UINT8 Data;
} GIOINBDC_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* GIOCDTTHROTTLE_IIO_DFX_IOSF_REG supported on:                              */
/*       BDX (0x40033204)                                                     */
/* Register default value:              0x00000000                            */
#define GIOCDTTHROTTLE_IIO_DFX_IOSF_REG 0x12034204

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * This register controls the PCIe throttling behavior through the control of 
 * available credits. 
 */
typedef union {
  struct {
    UINT32 nprh : 6;
    /* nprh - Bits[5:0], RWS_L, default = 6'b000000 
       Non Posted Request Header Throttling.Transaction layer will withhold the release 
       of credits to downstream devices until the credit available (in switch FIFO) 
       builds up to the value programmed here. 
       
       Notes:
       Locked by RSPLCK
     */
    UINT32 nprd : 8;
    /* nprd - Bits[13:6], RWS_L, default = 8'b00000000 
       Non Posted Request Data Throttling.Transaction layer will withhold the release 
       of credits to downstream devices until the credit available (in switch FIFO) 
       builds up to the value programmed here. 
       
       Notes:
       Locked by RSPLCK
     */
    UINT32 prh : 6;
    /* prh - Bits[19:14], RWS_L, default = 6'b000000 
       Posted Request Header Throttling.Transaction layer will withhold the release of 
       credits to downstream devices until the credit available (in switch FIFO) builds 
       up to the value programmed here. 
       
       Notes:
       Locked by RSPLCK
     */
    UINT32 prd : 8;
    /* prd - Bits[27:20], RWS_L, default = 8'b00000000 
       Posted Request Data Throttling.Transaction layer will withhold the release of 
       credits to downstream devices until the credit available (in switch FIFO) builds 
       up to the value programmed here. 
       
       Notes:
       Locked by RSPLCK
     */
    UINT32 throttle_resp_dis : 1;
    /* throttle_resp_dis - Bits[28:28], RWS_L, default = 1'b0 
       Notes:
       Locked by RSPLCK
     */
    UINT32 rsvd : 3;
    /* rsvd - Bits[31:29], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} GIOCDTTHROTTLE_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* GIOTHR_IIO_DFX_IOSF_REG supported on:                                      */
/*       BDX (0x10033208)                                                     */
/* Register default value:              0xCA                                  */
#define GIOTHR_IIO_DFX_IOSF_REG 0x12031208

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * This register controls PCIe throttling through the use of the DFx Response Logic 
 * Function. 
 */
typedef union {
  struct {
    UINT8 start_sel : 4;
    /* start_sel - Bits[3:0], RWS_L, default = 4'b1010 
       Selects the event/function to be used as the drl_start_req in the Response Logic 
       Function described in Section 2.3. 
       
       Notes:
       Locked by RSPLCK
     */
    UINT8 stop_sel : 4;
    /* stop_sel - Bits[7:4], RWS_L, default = 4'b1100 
       Selects the event/function to be used as the drl_stop_req in the Response Logic 
       Function described in Section 2.3. 
       
       Notes:
       Locked by RSPLCK
     */
  } Bits;
  UINT8 Data;
} GIOTHR_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* PXPTGTTHROTTLE_IIO_DFX_IOSF_REG supported on:                              */
/*       BDX (0x10033210)                                                     */
/* Register default value:              0x00                                  */
#define PXPTGTTHROTTLE_IIO_DFX_IOSF_REG 0x12031210

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * generated by critter 06_3_0x210
 */
typedef union {
  struct {
    UINT8 override_val : 4;
    /* override_val - Bits[3:0], RW, default = 4'b0000  */
    UINT8 override_en : 1;
    /* override_en - Bits[4:4], RW, default = 1'b0  */
    UINT8 rsvd : 3;
    /* rsvd - Bits[7:5], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT8 Data;
} PXPTGTTHROTTLE_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* DIOEINJ_IIO_DFX_IOSF_REG supported on:                                     */
/*       BDX (0x40033214)                                                     */
/* Register default value:              0x00000000                            */
#define DIOEINJ_IIO_DFX_IOSF_REG 0x12034214

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * generated by critter 06_3_0x214
 */
typedef union {
  struct {
    UINT32 parerr : 6;
    /* parerr - Bits[5:0], RW_L, default = 6'b000000 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 rsvd_6 : 1;
    /* rsvd_6 - Bits[6:6], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 pmeacsmsk : 1;
    /* pmeacsmsk - Bits[7:7], RWS_L, default = 1'b0 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 atomicaddrmsk : 1;
    /* atomicaddrmsk - Bits[8:8], RW_L, default = 1'b0 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 rsvd_9 : 23;
    /* rsvd_9 - Bits[31:9], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} DIOEINJ_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* OBEINJCTL_IIO_DFX_IOSF_REG supported on:                                   */
/*       BDX (0x40033240)                                                     */
/* Register default value:              0x00000000                            */
#define OBEINJCTL_IIO_DFX_IOSF_REG 0x12034240

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * This register contains the error injection mask register to determine which bits 
 * get corrupted for error detection testing. 
 */
typedef union {
  struct {
    UINT32 aeilceninj : 1;
    /* aeilceninj - Bits[0:0], RWS_L, default = 1'b0 
       0: Disable error injection
       1: Enable error injection
       
       Notes:
       Locked by SPARELCK
     */
    UINT32 aeilcinj1 : 1;
    /* aeilcinj1 - Bits[1:1], RWS_L, default = 1'b0 
       0: Select EINJ0 response function
       1: Select EINJ1 response function
       
       Notes:
       Locked by SPARELCK
     */
    UINT32 rsvd : 30;
    /* rsvd - Bits[31:2], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} OBEINJCTL_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* SPARE_IIO_DFX_IOSF_REG supported on:                                       */
/*       BDX (0x40033248)                                                     */
/* Register default value:              0x003FF000                            */
#define SPARE_IIO_DFX_IOSF_REG 0x12034248

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * generated by critter 06_3_0x248
 */
typedef union {
  struct {
    UINT32 force_data_perr_once : 1;
    /* force_data_perr_once - Bits[0:0], RWS_LV, default = 1'b0  */
    UINT32 pmnak_idlecycle : 5;
    /* pmnak_idlecycle - Bits[5:1], RWS_L, default = 5'b00000 
       Notes:
       Locked by SPARELCK
     */
    UINT32 enable_gc2wakeupl1 : 1;
    /* enable_gc2wakeupl1 - Bits[6:6], RWS_L, default = 1'b0 
       Notes:
       Locked by SPARELCK
     */
    UINT32 enable_gc2controll1 : 1;
    /* enable_gc2controll1 - Bits[7:7], RWS_L, default = 1'b0 
       Notes:
       Locked by SPARELCK
     */
    UINT32 cgtt_sparebits : 4;
    /* cgtt_sparebits - Bits[11:8], RWS_L, default = 4'b0000 
       1
     */
    UINT32 txn_port_spare1 : 10;
    /* txn_port_spare1 - Bits[21:12], RWS_L, default = 10'b1111111111  */
    UINT32 txn_port_spare0 : 10;
    /* txn_port_spare0 - Bits[31:22], RWS_L, default = 10'b0000000000  */
  } Bits;
  UINT32 Data;
} SPARE_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* XPPRIVC1_IIO_DFX_IOSF_REG supported on:                                    */
/*       BDX (0x4003326C)                                                     */
/* Register default value:              0x00000355                            */
#define XPPRIVC1_IIO_DFX_IOSF_REG 0x1203426C

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * generated by critter 06_3_0x26c
 */
typedef union {
  struct {
    UINT32 bwmsirevalen : 1;
    /* bwmsirevalen - Bits[0:0], RWS, default = 1'b1  */
    UINT32 bwmsiclapsen : 1;
    /* bwmsiclapsen - Bits[1:1], RWS, default = 1'b0  */
    UINT32 pmmsirevalen : 1;
    /* pmmsirevalen - Bits[2:2], RWS, default = 1'b1  */
    UINT32 pmmsiclapsen : 1;
    /* pmmsiclapsen - Bits[3:3], RWS, default = 1'b0  */
    UINT32 hpmsirevalen : 1;
    /* hpmsirevalen - Bits[4:4], RWS, default = 1'b1  */
    UINT32 hpmsiclapsen : 1;
    /* hpmsiclapsen - Bits[5:5], RWS, default = 1'b0 
       1
     */
    UINT32 aermsirevalen : 1;
    /* aermsirevalen - Bits[6:6], RWS, default = 1'b1  */
    UINT32 aermsiclapsen : 1;
    /* aermsiclapsen - Bits[7:7], RWS, default = 1'b0  */
    UINT32 mmcapen : 1;
    /* mmcapen - Bits[8:8], RWS, default = 1'b1  */
    UINT32 lermsirevalen : 1;
    /* lermsirevalen - Bits[9:9], RWS, default = 1'b1  */
    UINT32 lermsiclapsen : 1;
    /* lermsiclapsen - Bits[10:10], RWS, default = 1'b0  */
    UINT32 rsvd : 21;
    /* rsvd - Bits[31:11], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} XPPRIVC1_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* TXN_LAYER_DBG_MUX_SWIZ_SEL0_IIO_DFX_IOSF_REG supported on:                 */
/*       BDX (0x40033280)                                                     */
/* Register default value:              0x00000000                            */
#define TXN_LAYER_DBG_MUX_SWIZ_SEL0_IIO_DFX_IOSF_REG 0x12034280

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * This register selects which set of iistx/iittx debug signal sets drives the 
 * debug ring output of the transaction layer. 
 */
typedef union {
  struct {
    UINT32 dbg_ev_swiz_ln_sel_0 : 4;
    /* dbg_ev_swiz_ln_sel_0 - Bits[3:0], RWS_L, default = 4'b0000 
       Selects the source for byte lane 0 from the 9 internal debug bus lanes.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbg_ev_swiz_ln_sel_1 : 4;
    /* dbg_ev_swiz_ln_sel_1 - Bits[7:4], RWS_L, default = 4'b0000 
       Selects the source for byte lane 1 from the 9 internal debug bus lanes.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbg_ev_swiz_ln_sel_2 : 4;
    /* dbg_ev_swiz_ln_sel_2 - Bits[11:8], RWS_L, default = 4'b0000 
       Selects the source for byte lane 2 from the 9 internal debug bus lanes.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbg_ev_swiz_ln_sel_3 : 4;
    /* dbg_ev_swiz_ln_sel_3 - Bits[15:12], RWS_L, default = 4'b0000 
       Selects the source for byte lane 3 from the 9 internal debug bus lanes.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbg_ev_swiz_ln_sel_4 : 4;
    /* dbg_ev_swiz_ln_sel_4 - Bits[19:16], RWS_L, default = 4'b0000 
       Selects the source for byte lane 4 from the 9 internal debug bus lanes.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbg_ev_swiz_ln_sel_5 : 4;
    /* dbg_ev_swiz_ln_sel_5 - Bits[23:20], RWS_L, default = 4'b0000 
       Selects the source for byte lane 5 from the 9 internal debug bus lanes.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbg_ev_swiz_ln_sel_6 : 4;
    /* dbg_ev_swiz_ln_sel_6 - Bits[27:24], RWS_L, default = 4'b0000 
       Selects the source for byte lane 6 from the 9 internal debug bus lanes.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbg_ev_swiz_ln_sel_7 : 4;
    /* dbg_ev_swiz_ln_sel_7 - Bits[31:28], RWS_L, default = 4'b0000 
       Selects the source for byte lane 7 from the 9 internal debug bus lanes.
       Notes:
       Locked by DBGBUSLCK
     */
  } Bits;
  UINT32 Data;
} TXN_LAYER_DBG_MUX_SWIZ_SEL0_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* TXN_LAYER_DBG_MUX_SWIZ_SEL1_IIO_DFX_IOSF_REG supported on:                 */
/*       BDX (0x40033284)                                                     */
/* Register default value:              0x00000000                            */
#define TXN_LAYER_DBG_MUX_SWIZ_SEL1_IIO_DFX_IOSF_REG 0x12034284

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * This register selects which set of iistx/iittx debug signal sets drives the 
 * debug ring output of the transaction layer. 
 */
typedef union {
  struct {
    UINT32 dbg_ev_swiz_ln_sel_8 : 4;
    /* dbg_ev_swiz_ln_sel_8 - Bits[3:0], RWS_L, default = 4'b0000 
       Selects the source for byte lane 8 from the 9 internal debug bus lanes.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbg_bridge_signal_sel : 4;
    /* dbg_bridge_signal_sel - Bits[7:4], RWS_L, default = 4'b0000 
       selects the source for the bits 0 to 31
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbg_bridge_ip_src_sel : 3;
    /* dbg_bridge_ip_src_sel - Bits[10:8], RWS_L, default = 3'b000 
       selects the source
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 rsvd_11 : 13;
    /* rsvd_11 - Bits[23:11], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 cto0_sel : 2;
    /* cto0_sel - Bits[25:24], RWS_L, default = 2'b00 
       Bit-mask to select which IOU CTO source propagates through to the CTO.
       [1] - enable for outbound header match
       [0] - enable for inbound header match
       Locked by DBGBUSLCK
     */
    UINT32 rsvd_26 : 4;
    /* rsvd_26 - Bits[29:26], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 xor_mode : 1;
    /* xor_mode - Bits[30:30], RWS_L, default = 1'b0 
       Puts the debug muxes into XOR mode instead of MUX mode for scanout coverage.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbg_mux_en : 1;
    /* dbg_mux_en - Bits[31:31], RWS_L, default = 1'b0 
       Turns on the debug muxes (clocks, etc).
       Notes:
       Locked by DBGBUSLCK
     */
  } Bits;
  UINT32 Data;
} TXN_LAYER_DBG_MUX_SWIZ_SEL1_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* TXN_LAYER_DBG_MUX_INT_SEL0_IIO_DFX_IOSF_REG supported on:                  */
/*       BDX (0x400332A8)                                                     */
/* Register default value:              0x00000000                            */
#define TXN_LAYER_DBG_MUX_INT_SEL0_IIO_DFX_IOSF_REG 0x120342A8

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * This register selects which set of iistx/iittx debug signal sets will be muxed 
 * onto the internal debug bus of the transaction layer. 
 */
typedef union {
  struct {
    UINT32 dbg_ev_set_ln_sel_0 : 6;
    /* dbg_ev_set_ln_sel_0 - Bits[5:0], RWS_L, default = 6'b000000 
       Selects the source for byte lane 0 from each debug set.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbg_ev_set_ln_sel_1 : 6;
    /* dbg_ev_set_ln_sel_1 - Bits[11:6], RWS_L, default = 6'b000000 
       Selects the source for byte lane 1 from each debug set.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbg_ev_set_ln_sel_2 : 6;
    /* dbg_ev_set_ln_sel_2 - Bits[17:12], RWS_L, default = 6'b000000 
       Selects the source for byte lane 2 from each debug set.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbg_ev_set_ln_sel_3 : 6;
    /* dbg_ev_set_ln_sel_3 - Bits[23:18], RWS_L, default = 6'b000000 
       Selects the source for byte lane 3 from each debug set.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbg_ev_set_ln_sel_4 : 6;
    /* dbg_ev_set_ln_sel_4 - Bits[29:24], RWS_L, default = 6'b000000 
       Selects the source for byte lane 4 from each debug set.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 rsvd : 2;
    /* rsvd - Bits[31:30], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} TXN_LAYER_DBG_MUX_INT_SEL0_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* TXN_LAYER_DBG_MUX_INT_SEL1_IIO_DFX_IOSF_REG supported on:                  */
/*       BDX (0x400332AC)                                                     */
/* Register default value:              0x00000000                            */
#define TXN_LAYER_DBG_MUX_INT_SEL1_IIO_DFX_IOSF_REG 0x120342AC

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * This register selects which set of iistx/iittx debug signal sets will be muxed 
 * onto the internal debug bus of the transaction layer. 
 */
typedef union {
  struct {
    UINT32 dbg_ev_set_ln_sel_5 : 6;
    /* dbg_ev_set_ln_sel_5 - Bits[5:0], RWS_L, default = 6'b000000 
       Selects the source for byte lane 5 from each debug set.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbg_ev_set_ln_sel_6 : 6;
    /* dbg_ev_set_ln_sel_6 - Bits[11:6], RWS_L, default = 6'b000000 
       Selects the source for byte lane 6 from each debug set.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbg_ev_set_ln_sel_7 : 6;
    /* dbg_ev_set_ln_sel_7 - Bits[17:12], RWS_L, default = 6'b000000 
       Selects the source for byte lane 7 from each debug set.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbg_ev_set_ln_sel_8 : 6;
    /* dbg_ev_set_ln_sel_8 - Bits[23:18], RWS_L, default = 6'b000000 
       Selects the source for byte lane 8 from each debug set.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 rsvd : 8;
    /* rsvd - Bits[31:24], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} TXN_LAYER_DBG_MUX_INT_SEL1_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* DIOHMATH0_IIO_DFX_IOSF_REG supported on:                                   */
/*       BDX (0x400332D0)                                                     */
/* Register default value:              0x00000000                            */
#define DIOHMATH0_IIO_DFX_IOSF_REG 0x120342D0

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * This register contains the Least Significant Dword (LSD) of a 128-bit match 
 * register that is used to compare inbound transactions finding a unique match. 
 * This register is used with the mask register to produced ranges of searches for 
 * particular types of transactions. The output of the match logic is connected to 
 * XPCTO0. 
 */
typedef union {
  struct {
    UINT32 hmat0 : 8;
    /* hmat0 - Bits[7:0], RWS_L, default = 8'b00000000 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 hmat1 : 8;
    /* hmat1 - Bits[15:8], RWS_L, default = 8'b00000000 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 hmat2 : 8;
    /* hmat2 - Bits[23:16], RWS_L, default = 8'b00000000 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 hmat3 : 8;
    /* hmat3 - Bits[31:24], RWS_L, default = 8'b00000000 
       Notes:
       Locked by DBGBUSLCK
     */
  } Bits;
  UINT32 Data;
} DIOHMATH0_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* DIOHMATH1_IIO_DFX_IOSF_REG supported on:                                   */
/*       BDX (0x400332D4)                                                     */
/* Register default value:              0x00000000                            */
#define DIOHMATH1_IIO_DFX_IOSF_REG 0x120342D4

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * This register contains the Least Significant Dword (LSD) +1 of a 128-bit match 
 * register that is used to compare transactions finding a unique match. This 
 * register is used with the mask register to produced ranges of searches for 
 * particular types of transactions. 
 */
typedef union {
  struct {
    UINT32 hmat0 : 8;
    /* hmat0 - Bits[7:0], RWS_L, default = 8'b00000000 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 hmat1 : 8;
    /* hmat1 - Bits[15:8], RWS_L, default = 8'b00000000 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 hmat2 : 8;
    /* hmat2 - Bits[23:16], RWS_L, default = 8'b00000000 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 hmat3 : 8;
    /* hmat3 - Bits[31:24], RWS_L, default = 8'b00000000 
       Notes:
       Locked by DBGBUSLCK
     */
  } Bits;
  UINT32 Data;
} DIOHMATH1_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* DIOHMATH2_IIO_DFX_IOSF_REG supported on:                                   */
/*       BDX (0x400332D8)                                                     */
/* Register default value:              0x00000000                            */
#define DIOHMATH2_IIO_DFX_IOSF_REG 0x120342D8

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * This register contains the Most Significant Dword (MSD) - 1 of a 128-bit match 
 * register that is used to compare transactions finding a unique match. This 
 * register is used with the mask register to produced ranges of searches for 
 * particular types of transactions. 
 */
typedef union {
  struct {
    UINT32 hmat0 : 8;
    /* hmat0 - Bits[7:0], RWS_L, default = 8'b00000000 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 hmat1 : 8;
    /* hmat1 - Bits[15:8], RWS_L, default = 8'b00000000 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 hmat2 : 8;
    /* hmat2 - Bits[23:16], RWS_L, default = 8'b00000000 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 hmat3 : 8;
    /* hmat3 - Bits[31:24], RWS_L, default = 8'b00000000 
       Notes:
       Locked by DBGBUSLCK
     */
  } Bits;
  UINT32 Data;
} DIOHMATH2_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* DIOHMATH3_IIO_DFX_IOSF_REG supported on:                                   */
/*       BDX (0x400332DC)                                                     */
/* Register default value:              0x00000000                            */
#define DIOHMATH3_IIO_DFX_IOSF_REG 0x120342DC

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * This register contains the Most Significant Dword (MSD) of a 128-bit match 
 * register that is used to compare transactions finding a unique match. This 
 * register is used with the mask register to produced ranges of searches for 
 * particular types of transactions. 
 */
typedef union {
  struct {
    UINT32 hmat0 : 8;
    /* hmat0 - Bits[7:0], RWS_L, default = 8'b00000000 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 hmat1 : 8;
    /* hmat1 - Bits[15:8], RWS_L, default = 8'b00000000 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 hmat2 : 8;
    /* hmat2 - Bits[23:16], RWS_L, default = 8'b00000000 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 hmat3 : 8;
    /* hmat3 - Bits[31:24], RWS_L, default = 8'b00000000 
       Notes:
       Locked by DBGBUSLCK
     */
  } Bits;
  UINT32 Data;
} DIOHMATH3_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* DIOHMASK0_IIO_DFX_IOSF_REG supported on:                                   */
/*       BDX (0x400332E0)                                                     */
/* Register default value:              0x00000000                            */
#define DIOHMASK0_IIO_DFX_IOSF_REG 0x120342E0

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * The header bits to be used in matching are selected by the mask bits in this 
 * register. A zero in a mask bit position causes the corresponding bit in the 
 * header to be ignored. A one in a mask bit position indicates that the 
 * corresponding bit in the header must match the value of the same bit in the 
 * Match register for that bit to be considered to have matched. Pattern match out 
 * is asserted only if all enabled bit match (AND matching). If all mask bits are 
 * 0, MatchOut is 0. 
 */
typedef union {
  struct {
    UINT32 hmat0 : 8;
    /* hmat0 - Bits[7:0], RWS_L, default = 8'b00000000 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 hmat1 : 8;
    /* hmat1 - Bits[15:8], RWS_L, default = 8'b00000000 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 hmat2 : 8;
    /* hmat2 - Bits[23:16], RWS_L, default = 8'b00000000 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 hmat3 : 8;
    /* hmat3 - Bits[31:24], RWS_L, default = 8'b00000000 
       Notes:
       Locked by DBGBUSLCK
     */
  } Bits;
  UINT32 Data;
} DIOHMASK0_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* DIOHMASK1_IIO_DFX_IOSF_REG supported on:                                   */
/*       BDX (0x400332E4)                                                     */
/* Register default value:              0x00000000                            */
#define DIOHMASK1_IIO_DFX_IOSF_REG 0x120342E4

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * This register contains the mask bits to determine which fields of bits the match 
 * register is effective. 
 */
typedef union {
  struct {
    UINT32 hmat0 : 8;
    /* hmat0 - Bits[7:0], RWS_L, default = 8'b00000000 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 hmat1 : 8;
    /* hmat1 - Bits[15:8], RWS_L, default = 8'b00000000 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 hmat2 : 8;
    /* hmat2 - Bits[23:16], RWS_L, default = 8'b00000000 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 hmat3 : 8;
    /* hmat3 - Bits[31:24], RWS_L, default = 8'b00000000 
       Notes:
       Locked by DBGBUSLCK
     */
  } Bits;
  UINT32 Data;
} DIOHMASK1_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* DIOHMASK2_IIO_DFX_IOSF_REG supported on:                                   */
/*       BDX (0x400332E8)                                                     */
/* Register default value:              0x00000000                            */
#define DIOHMASK2_IIO_DFX_IOSF_REG 0x120342E8

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * This register contains the mask bits to determine which fields of bits the match 
 * register is effective. 
 */
typedef union {
  struct {
    UINT32 hmat0 : 8;
    /* hmat0 - Bits[7:0], RWS_L, default = 8'b00000000 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 hmat1 : 8;
    /* hmat1 - Bits[15:8], RWS_L, default = 8'b00000000 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 hmat2 : 8;
    /* hmat2 - Bits[23:16], RWS_L, default = 8'b00000000 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 hmat3 : 8;
    /* hmat3 - Bits[31:24], RWS_L, default = 8'b00000000 
       Notes:
       Locked by DBGBUSLCK
     */
  } Bits;
  UINT32 Data;
} DIOHMASK2_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* DIOHMASK3_IIO_DFX_IOSF_REG supported on:                                   */
/*       BDX (0x400332EC)                                                     */
/* Register default value:              0x00000000                            */
#define DIOHMASK3_IIO_DFX_IOSF_REG 0x120342EC

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * This register contains the mask bits to determine which fields of bits the match 
 * register is effective. 
 */
typedef union {
  struct {
    UINT32 hmat0 : 8;
    /* hmat0 - Bits[7:0], RWS_L, default = 8'b00000000 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 hmat1 : 8;
    /* hmat1 - Bits[15:8], RWS_L, default = 8'b00000000 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 hmat2 : 8;
    /* hmat2 - Bits[23:16], RWS_L, default = 8'b00000000 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 hmat3 : 8;
    /* hmat3 - Bits[31:24], RWS_L, default = 8'b00000000 
       Notes:
       Locked by DBGBUSLCK
     */
  } Bits;
  UINT32 Data;
} DIOHMASK3_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* PXPCTRL_IIO_DFX_IOSF_REG supported on:                                     */
/*       BDX (0x400332F0)                                                     */
/* Register default value:              0x03607400                            */
#define PXPCTRL_IIO_DFX_IOSF_REG 0x120342F0

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * generated by critter 06_3_0x2f0
 */
typedef union {
  struct {
    UINT32 devhide : 1;
    /* devhide - Bits[0:0], RW, default = 1'b0  */
    UINT32 dis_apic_eoi : 1;
    /* dis_apic_eoi - Bits[1:1], RW, default = 1'b0  */
    UINT32 dis_vpp : 1;
    /* dis_vpp - Bits[2:2], RW, default = 1'b0  */
    UINT32 vpp : 4;
    /* vpp - Bits[6:3], RW, default = 4'b0000  */
    UINT32 dis_inb_cfg : 1;
    /* dis_inb_cfg - Bits[7:7], RW_O, default = 1'b0  */
    UINT32 msihpen : 1;
    /* msihpen - Bits[8:8], RW, default = 1'b0  */
    UINT32 msipmen : 1;
    /* msipmen - Bits[9:9], RW, default = 1'b0  */
    UINT32 coalesce_en : 1;
    /* coalesce_en - Bits[10:10], RW, default = 1'b1  */
    UINT32 cf : 1;
    /* cf - Bits[11:11], RW_L, default = 1'b0 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 tg256b_en : 1;
    /* tg256b_en - Bits[12:12], RW, default = 1'b1  */
    UINT32 interleave_en : 1;
    /* interleave_en - Bits[13:13], RW, default = 1'b1  */
    UINT32 stream_interleave_check_en : 1;
    /* stream_interleave_check_en - Bits[14:14], RW, default = 1'b1  */
    UINT32 dzlmr : 1;
    /* dzlmr - Bits[15:15], RW_L, default = 1'b0 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dzlir : 1;
    /* dzlir - Bits[16:16], RW_L, default = 1'b0 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dzlcr : 1;
    /* dzlcr - Bits[17:17], RW_L, default = 1'b0 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dzlmw : 1;
    /* dzlmw - Bits[18:18], RW_L, default = 1'b0 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dzliw : 1;
    /* dzliw - Bits[19:19], RW_L, default = 1'b0 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dzlcw : 1;
    /* dzlcw - Bits[20:20], RW_L, default = 1'b0 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 maltlp_en : 1;
    /* maltlp_en - Bits[21:21], RW_L, default = 1'b1 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 timeout_enable : 1;
    /* timeout_enable - Bits[22:22], RW, default = 1'b1  */
    UINT32 timeout_enable_cfg : 1;
    /* timeout_enable_cfg - Bits[23:23], RW, default = 1'b0  */
    UINT32 coalesce_mode : 2;
    /* coalesce_mode - Bits[25:24], RW, default = 2'b11  */
    UINT32 read_interlock : 1;
    /* read_interlock - Bits[26:26], RW, default = 1'b0  */
    UINT32 dis_toggle_pop_pri : 1;
    /* dis_toggle_pop_pri - Bits[27:27], RW, default = 1'b0  */
    UINT32 gpo : 1;
    /* gpo - Bits[28:28], RW, default = 1'b0  */
    UINT32 msifaten : 1;
    /* msifaten - Bits[29:29], RW, default = 1'b0  */
    UINT32 msinfaten : 1;
    /* msinfaten - Bits[30:30], RW, default = 1'b0  */
    UINT32 msicoren : 1;
    /* msicoren - Bits[31:31], RW, default = 1'b0  */
  } Bits;
  UINT32 Data;
} PXPCTRL_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* PXPCTRL3_IIO_DFX_IOSF_REG supported on:                                    */
/*       BDX (0x400332F4)                                                     */
/* Register default value:              0x00000006                            */
#define PXPCTRL3_IIO_DFX_IOSF_REG 0x120342F4

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * generated by critter 06_3_0x2f4
 */
typedef union {
  struct {
    UINT32 abort_c_if_non_d0 : 1;
    /* abort_c_if_non_d0 - Bits[0:0], RW_L, default = 1'b0 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 abort_np_if_non_d0 : 1;
    /* abort_np_if_non_d0 - Bits[1:1], RW_L, default = 1'b1 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 abort_p_if_non_d0 : 1;
    /* abort_p_if_non_d0 - Bits[2:2], RW_L, default = 1'b1 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 en_abort_in_d1 : 1;
    /* en_abort_in_d1 - Bits[3:3], RW_L, default = 1'b0 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 en_abort_in_d2 : 1;
    /* en_abort_in_d2 - Bits[4:4], RW_L, default = 1'b0 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 en_abort_in_d3 : 1;
    /* en_abort_in_d3 - Bits[5:5], RW_L, default = 1'b0 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 rsvd : 26;
    /* rsvd - Bits[31:6], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} PXPCTRL3_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* DIO_OB_HMATCH0_IIO_DFX_IOSF_REG supported on:                              */
/*       BDX (0x40033330)                                                     */
/* Register default value:              0x00000000                            */
#define DIO_OB_HMATCH0_IIO_DFX_IOSF_REG 0x12034330

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * This register contains Dword 0 [31:0] of the 128b match register for outbound 
 * headers. 
 */
typedef union {
  struct {
    UINT32 hmatch : 32;
    /* hmatch - Bits[31:0], RWS_L, default = 32'b00000000000000000000000000000000 
       Notes:
       Locked by DBGBUSLCK
     */
  } Bits;
  UINT32 Data;
} DIO_OB_HMATCH0_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* DIO_OB_HMATCH1_IIO_DFX_IOSF_REG supported on:                              */
/*       BDX (0x40033334)                                                     */
/* Register default value:              0x00000000                            */
#define DIO_OB_HMATCH1_IIO_DFX_IOSF_REG 0x12034334

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * This register contains Dword 1 [63:32] of the 128b match register for outbound 
 * headers. 
 */
typedef union {
  struct {
    UINT32 hmatch : 32;
    /* hmatch - Bits[31:0], RWS_L, default = 32'b00000000000000000000000000000000 
       Notes:
       Locked by DBGBUSLCK
     */
  } Bits;
  UINT32 Data;
} DIO_OB_HMATCH1_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* DIO_OB_HMATCH2_IIO_DFX_IOSF_REG supported on:                              */
/*       BDX (0x40033338)                                                     */
/* Register default value:              0x00000000                            */
#define DIO_OB_HMATCH2_IIO_DFX_IOSF_REG 0x12034338

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * This register contains Dword 2 [95:64] of the 128b match register for outbound 
 * headers. 
 */
typedef union {
  struct {
    UINT32 hmatch : 32;
    /* hmatch - Bits[31:0], RWS_L, default = 32'b00000000000000000000000000000000 
       Notes:
       Locked by DBGBUSLCK
     */
  } Bits;
  UINT32 Data;
} DIO_OB_HMATCH2_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* DIO_OB_HMATCH3_IIO_DFX_IOSF_REG supported on:                              */
/*       BDX (0x4003333C)                                                     */
/* Register default value:              0x00000000                            */
#define DIO_OB_HMATCH3_IIO_DFX_IOSF_REG 0x1203433C

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * This register contains Dword 3 [127:96] of the 128b match register for outbound 
 * headers. 
 */
typedef union {
  struct {
    UINT32 hmatch : 32;
    /* hmatch - Bits[31:0], RWS_L, default = 32'b00000000000000000000000000000000 
       Notes:
       Locked by DBGBUSLCK
     */
  } Bits;
  UINT32 Data;
} DIO_OB_HMATCH3_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* DIO_OB_HMASK0_IIO_DFX_IOSF_REG supported on:                               */
/*       BDX (0x40033340)                                                     */
/* Register default value:              0x00000000                            */
#define DIO_OB_HMASK0_IIO_DFX_IOSF_REG 0x12034340

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * This register contains Dword 0 [31:0] of the 128b mask register for outbound 
 * headers. 
 */
typedef union {
  struct {
    UINT32 hmask : 32;
    /* hmask - Bits[31:0], RWS_L, default = 32'b00000000000000000000000000000000 
       Notes:
       Locked by DBGBUSLCK
     */
  } Bits;
  UINT32 Data;
} DIO_OB_HMASK0_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* DIO_OB_HMASK1_IIO_DFX_IOSF_REG supported on:                               */
/*       BDX (0x40033344)                                                     */
/* Register default value:              0x00000000                            */
#define DIO_OB_HMASK1_IIO_DFX_IOSF_REG 0x12034344

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * This register contains Dword 1 [63:32] of the 128b mask register for outbound 
 * headers. 
 */
typedef union {
  struct {
    UINT32 hmask : 32;
    /* hmask - Bits[31:0], RWS_L, default = 32'b00000000000000000000000000000000 
       Notes:
       Locked by DBGBUSLCK
     */
  } Bits;
  UINT32 Data;
} DIO_OB_HMASK1_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* DIO_OB_HMASK2_IIO_DFX_IOSF_REG supported on:                               */
/*       BDX (0x40033348)                                                     */
/* Register default value:              0x00000000                            */
#define DIO_OB_HMASK2_IIO_DFX_IOSF_REG 0x12034348

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * This register contains Dword 2 [95:64] of the 128b mask register for outbound 
 * headers. 
 */
typedef union {
  struct {
    UINT32 hmask : 32;
    /* hmask - Bits[31:0], RWS_L, default = 32'b00000000000000000000000000000000 
       Notes:
       Locked by DBGBUSLCK
     */
  } Bits;
  UINT32 Data;
} DIO_OB_HMASK2_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* DIO_OB_HMASK3_IIO_DFX_IOSF_REG supported on:                               */
/*       BDX (0x4003334C)                                                     */
/* Register default value:              0x00000000                            */
#define DIO_OB_HMASK3_IIO_DFX_IOSF_REG 0x1203434C

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * This register contains Dword 3 [127:96] of the 128b mask register for outbound 
 * headers. 
 */
typedef union {
  struct {
    UINT32 hmask : 32;
    /* hmask - Bits[31:0], RWS_L, default = 32'b00000000000000000000000000000000 
       Notes:
       Locked by DBGBUSLCK
     */
  } Bits;
  UINT32 Data;
} DIO_OB_HMASK3_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* PXPHDRXENG_IIO_DFX_IOSF_REG supported on:                                  */
/*       BDX (0x4003337C)                                                     */
/* Register default value:              0x00000000                            */
#define PXPHDRXENG_IIO_DFX_IOSF_REG 0x1203437C

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * This register contains the bits to translate the address and attributes field.
 */
typedef union {
  struct {
    UINT32 xor_ttype : 5;
    /* xor_ttype - Bits[4:0], RW_L, default = 5'b00000 
       When translation is enabled by one of the xxx_TTYPE_XOR_EN, this field is XOR'd 
       with the corresponding TTYPE field 
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 rsvd_5 : 4;
    /* rsvd_5 - Bits[8:5], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 xor_mem_cfg_addr : 4;
    /* xor_mem_cfg_addr - Bits[12:9], RW_L, default = 4'b0000 
       When translation is enabled by MEM_XOR_EN or CFG_XOR_EN, this field is XOR'd 
       with bits [31:28] of the Mem or CFG Address 
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 xor_io_addr : 3;
    /* xor_io_addr - Bits[15:13], RW_L, default = 3'b000 
       When translation is enabled by IO_ADDR_XOR_EN, this field is XOR'd with bits 
       [15:13] of the IO Address 
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 cfg_ttype_xor_en : 1;
    /* cfg_ttype_xor_en - Bits[16:16], RW_L, default = 1'b0 
       0: no translation
       1: transaction type is XOR'd with XOR_TTYPE on CFG space transactions
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 io_ttype_xor_en : 1;
    /* io_ttype_xor_en - Bits[17:17], RW_L, default = 1'b0 
       0: no translation
       1: transaction type is XOR'd with XOR_TTYPE on IO space transactions
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 mem_ttype_xor_en : 1;
    /* mem_ttype_xor_en - Bits[18:18], RW_L, default = 1'b0 
       0: no translation
       1: transaction type is XOR'd with XOR_TTYPE on Memory space transactions
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 cfg_addr_xor_en : 1;
    /* cfg_addr_xor_en - Bits[19:19], RW_L, default = 1'b0 
       0: no translation
       1: CFG Address bits [31:28] are XOR'd with XOR_MEM_CFG_ADDR
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 io_addr_xor_en : 1;
    /* io_addr_xor_en - Bits[20:20], RW_L, default = 1'b0 
       0: no translation
       1: IO Address bits [15:13] are XOR'd with XOR_IO_ADDR
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 mem_addr_xor_en : 1;
    /* mem_addr_xor_en - Bits[21:21], RW_L, default = 1'b0 
       0: no translation
       1: Mem Address bits [31:28] are XOR'd with XOR_MEM_CFG_ADDR
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 memwrmodification_en : 1;
    /* memwrmodification_en - Bits[22:22], RW_L, default = 1'b0 
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 drop_completions_en : 1;
    /* drop_completions_en - Bits[23:23], RW_L, default = 1'b0 
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 disable_credit_check_en : 1;
    /* disable_credit_check_en - Bits[24:24], RW_L, default = 1'b0 
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 memwrmodification_3dw : 1;
    /* memwrmodification_3dw - Bits[25:25], RW_L, default = 1'b0 
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 datamodification_3dw : 1;
    /* datamodification_3dw - Bits[26:26], RW_L, default = 1'b0 
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 rsvd_27 : 5;
    /* rsvd_27 - Bits[31:27], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} PXPHDRXENG_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* PXPHDRXENG1_IIO_DFX_IOSF_REG supported on:                                 */
/*       BDX (0x40033380)                                                     */
/* Register default value:              0x00000000                            */
#define PXPHDRXENG1_IIO_DFX_IOSF_REG 0x12034380

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * generated by critter 06_3_0x380
 */
typedef union {
  struct {
    UINT32 xor_tc : 3;
    /* xor_tc - Bits[2:0], RW_L, default = 3'b000  */
    UINT32 io_tc_xor_en : 1;
    /* io_tc_xor_en - Bits[3:3], RW_L, default = 1'b0  */
    UINT32 cfg_tc_xor_en : 1;
    /* cfg_tc_xor_en - Bits[4:4], RW_L, default = 1'b0  */
    UINT32 mem_tc_xor_en : 1;
    /* mem_tc_xor_en - Bits[5:5], RW_L, default = 1'b0  */
    UINT32 xor_attrib : 2;
    /* xor_attrib - Bits[7:6], RW_L, default = 2'b00  */
    UINT32 io_attrib_xor_en : 1;
    /* io_attrib_xor_en - Bits[8:8], RW_L, default = 1'b0  */
    UINT32 cfg_attrib_xor_en : 1;
    /* cfg_attrib_xor_en - Bits[9:9], RW_L, default = 1'b0  */
    UINT32 mem_attrib_xor_en : 1;
    /* mem_attrib_xor_en - Bits[10:10], RW_L, default = 1'b0  */
    UINT32 xor_mem_cfg_addr11_4 : 8;
    /* xor_mem_cfg_addr11_4 - Bits[18:11], RW_L, default = 8'b00000000  */
    UINT32 xor_mem_cfg_addr18_12 : 7;
    /* xor_mem_cfg_addr18_12 - Bits[25:19], RW_L, default = 7'b0000000  */
    UINT32 rsvd : 6;
    /* rsvd - Bits[31:26], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} PXPHDRXENG1_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* PSMICREDITREG0_IIO_DFX_IOSF_REG supported on:                              */
/*       BDX (0x40033500)                                                     */
/* Register default value:              0x00000000                            */
#define PSMICREDITREG0_IIO_DFX_IOSF_REG 0x12034500

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * generated by critter 06_3_0x500
 */
typedef union {
  struct {
    UINT32 prh_credit_used : 8;
    /* prh_credit_used - Bits[7:0], RW_LV, default = 8'b00000000 
       
       Notes:
       Locked by SPARELCK
     */
    UINT32 nprh_credit_used : 8;
    /* nprh_credit_used - Bits[15:8], RW_LV, default = 8'b00000000 
       
       Notes:
       Locked by SPARELCK
     */
    UINT32 nprh_credit_allocd : 8;
    /* nprh_credit_allocd - Bits[23:16], RW_LV, default = 8'b00000000 
       
       Notes:
       Locked by SPARELCK
     */
    UINT32 prh_credit_allocd : 8;
    /* prh_credit_allocd - Bits[31:24], RW_LV, default = 8'b00000000 
       
       Notes:
       Locked by SPARELCK
     */
  } Bits;
  UINT32 Data;
} PSMICREDITREG0_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* PSMICREDITREG1_IIO_DFX_IOSF_REG supported on:                              */
/*       BDX (0x40033504)                                                     */
/* Register default value:              0x00000000                            */
#define PSMICREDITREG1_IIO_DFX_IOSF_REG 0x12034504

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * generated by critter 06_3_0x504
 */
typedef union {
  struct {
    UINT32 cplh_credit_used : 8;
    /* cplh_credit_used - Bits[7:0], RW_LV, default = 8'b00000000 
       
       Notes:
       Locked by SPARELCK
     */
    UINT32 cplh_credit_allocd : 8;
    /* cplh_credit_allocd - Bits[15:8], RW_LV, default = 8'b00000000 
       
       Notes:
       Locked by SPARELCK
     */
    UINT32 rsvd : 16;
    /* rsvd - Bits[31:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} PSMICREDITREG1_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* PSMICREDITREG2_IIO_DFX_IOSF_REG supported on:                              */
/*       BDX (0x40033508)                                                     */
/* Register default value:              0x00000000                            */
#define PSMICREDITREG2_IIO_DFX_IOSF_REG 0x12034508

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * generated by critter 06_3_0x508
 */
typedef union {
  struct {
    UINT32 prd_credit_used : 12;
    /* prd_credit_used - Bits[11:0], RW_LV, default = 12'b000000000000 
       
       Notes:
       Locked by SPARELCK
     */
    UINT32 prd_credit_allocd : 12;
    /* prd_credit_allocd - Bits[23:12], RW_LV, default = 12'b000000000000 
       
       Notes:
       Locked by SPARELCK
     */
    UINT32 rsvd : 8;
    /* rsvd - Bits[31:24], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} PSMICREDITREG2_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* PSMICREDITREG3_IIO_DFX_IOSF_REG supported on:                              */
/*       BDX (0x4003350C)                                                     */
/* Register default value:              0x00000000                            */
#define PSMICREDITREG3_IIO_DFX_IOSF_REG 0x1203450C

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * generated by critter 06_3_0x50c
 */
typedef union {
  struct {
    UINT32 nprd_credit_used : 12;
    /* nprd_credit_used - Bits[11:0], RW_LV, default = 12'b000000000000 
       
       Notes:
       Locked by SPARELCK
     */
    UINT32 nprd_credit_allocd : 12;
    /* nprd_credit_allocd - Bits[23:12], RW_LV, default = 12'b000000000000 
       
       Notes:
       Locked by SPARELCK
     */
    UINT32 rsvd : 8;
    /* rsvd - Bits[31:24], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} PSMICREDITREG3_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* PSMICREDITREG4_IIO_DFX_IOSF_REG supported on:                              */
/*       BDX (0x40033510)                                                     */
/* Register default value:              0x00000000                            */
#define PSMICREDITREG4_IIO_DFX_IOSF_REG 0x12034510

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * generated by critter 06_3_0x510
 */
typedef union {
  struct {
    UINT32 cpld_credit_used : 12;
    /* cpld_credit_used - Bits[11:0], RW_LV, default = 12'b000000000000 
       
       Notes:
       Locked by SPARELCK
     */
    UINT32 cpld_credit_allocd : 12;
    /* cpld_credit_allocd - Bits[23:12], RW_LV, default = 12'b000000000000 
       
       Notes:
       Locked by SPARELCK
     */
    UINT32 rsvd : 8;
    /* rsvd - Bits[31:24], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} PSMICREDITREG4_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* PSMISPAREREG1_IIO_DFX_IOSF_REG supported on:                               */
/*       BDX (0x40033528)                                                     */
/* Register default value:              0x00000000                            */
#define PSMISPAREREG1_IIO_DFX_IOSF_REG 0x12034528

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * generated by critter 06_3_0x528
 */
typedef union {
  struct {
    UINT32 spare_reg_field : 16;
    /* spare_reg_field - Bits[15:0], RW_LV, default = 16'b0000000000000000 
       
       Notes:
       Locked by SPARELCK
     */
    UINT32 rsvd : 16;
    /* rsvd - Bits[31:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} PSMISPAREREG1_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* DIOTAGAVAILPSMI1_IIO_DFX_IOSF_REG supported on:                            */
/*       BDX (0x4003353C)                                                     */
/* Register default value:              0x00000000                            */
#define DIOTAGAVAILPSMI1_IIO_DFX_IOSF_REG 0x1203453C

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * generated by critter 06_3_0x53c
 */
typedef union {
  struct {
    UINT32 tag_avail_arb42 : 16;
    /* tag_avail_arb42 - Bits[15:0], RW_LV, default = 16'b0000000000000000 
       Notes:
       Locked by SPARELCK
     */
    UINT32 tag_avail_arb43 : 16;
    /* tag_avail_arb43 - Bits[31:16], RW_LV, default = 16'b0000000000000000 
       Notes:
       Locked by SPARELCK
     */
  } Bits;
  UINT32 Data;
} DIOTAGAVAILPSMI1_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* DIOTAGAVAILPSMI_IIO_DFX_IOSF_REG supported on:                             */
/*       BDX (0x40033540)                                                     */
/* Register default value:              0x00000000                            */
#define DIOTAGAVAILPSMI_IIO_DFX_IOSF_REG 0x12034540

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * generated by critter 06_3_0x540
 */
typedef union {
  struct {
    UINT32 tag_avail_arb40 : 16;
    /* tag_avail_arb40 - Bits[15:0], RW_LV, default = 16'b0000000000000000 
       Notes:
       Locked by SPARELCK
     */
    UINT32 tag_avail_arb41 : 16;
    /* tag_avail_arb41 - Bits[31:16], RW_LV, default = 16'b0000000000000000 
       Notes:
       Locked by SPARELCK
     */
  } Bits;
  UINT32 Data;
} DIOTAGAVAILPSMI_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* PXPDLLCREDITREG13_IIO_DFX_IOSF_REG supported on:                           */
/*       BDX (0x40033544)                                                     */
/* Register default value:              0x00B05800                            */
#define PXPDLLCREDITREG13_IIO_DFX_IOSF_REG 0x12034544

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * generated by critter 06_3_0x544
 */
typedef union {
  struct {
    UINT32 rsvd_0 : 8;
    /* rsvd_0 - Bits[7:0], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 swrf_num_prh_x8 : 8;
    /* swrf_num_prh_x8 - Bits[15:8], RWS_L, default = 8'b01011000  */
    UINT32 swrf_num_prh_x16 : 8;
    /* swrf_num_prh_x16 - Bits[23:16], RWS_L, default = 8'b10110000  */
    UINT32 rsvd_24 : 8;
    /* rsvd_24 - Bits[31:24], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} PXPDLLCREDITREG13_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* PXPDLLCREDITREG23_IIO_DFX_IOSF_REG supported on:                           */
/*       BDX (0x40033548)                                                     */
/* Register default value:              0x0000A854                            */
#define PXPDLLCREDITREG23_IIO_DFX_IOSF_REG 0x12034548

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * generated by critter 06_3_0x548
 */
typedef union {
  struct {
    UINT32 swrf_num_nprh_x8 : 8;
    /* swrf_num_nprh_x8 - Bits[7:0], RWS_L, default = 8'b01010100  */
    UINT32 swrf_num_nprh_x16 : 8;
    /* swrf_num_nprh_x16 - Bits[15:8], RWS_L, default = 8'b10101000  */
    UINT32 rsvd : 16;
    /* rsvd - Bits[31:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} PXPDLLCREDITREG23_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* PXPDLLCREDITREG33_IIO_DFX_IOSF_REG supported on:                           */
/*       BDX (0x4003354C)                                                     */
/* Register default value:              0x00000160                            */
#define PXPDLLCREDITREG33_IIO_DFX_IOSF_REG 0x1203454C

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * generated by critter 06_3_0x54c
 */
typedef union {
  struct {
    UINT32 swrf_num_prd_x8 : 12;
    /* swrf_num_prd_x8 - Bits[11:0], RWS_L, default = 12'b000101100000  */
    UINT32 rsvd : 20;
    /* rsvd - Bits[31:12], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} PXPDLLCREDITREG33_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* PXPDLLCREDITREG43_IIO_DFX_IOSF_REG supported on:                           */
/*       BDX (0x40033550)                                                     */
/* Register default value:              0x0000C000                            */
#define PXPDLLCREDITREG43_IIO_DFX_IOSF_REG 0x12034550

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * generated by critter 06_3_0x550
 */
typedef union {
  struct {
    UINT32 rsvd_0 : 12;
    /* rsvd_0 - Bits[11:0], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 swrf_num_nprd_x8 : 12;
    /* swrf_num_nprd_x8 - Bits[23:12], RWS_L, default = 12'b000000001100  */
    UINT32 rsvd_24 : 8;
    /* rsvd_24 - Bits[31:24], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} PXPDLLCREDITREG43_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* TAGSUSEDCNT_IIO_DFX_IOSF_REG supported on:                                 */
/*       BDX (0x40033898)                                                     */
/* Register default value:              0x00000000                            */
#define TAGSUSEDCNT_IIO_DFX_IOSF_REG 0x12034898

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * generated by critter 06_3_0x898
 */
typedef union {
  struct {
    UINT32 alltagsusedcnt : 32;
    /* alltagsusedcnt - Bits[31:0], RW, default = 32'b00000000000000000000000000000000  */
  } Bits;
  UINT32 Data;
} TAGSUSEDCNT_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* XPDFXSPAREREG_IIO_DFX_IOSF_REG supported on:                               */
/*       BDX (0x40033B40)                                                     */
/* Register default value:              0xC7D20082                            */
#define XPDFXSPAREREG_IIO_DFX_IOSF_REG 0x12034B40

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * generated by critter 06_3_0xb40
 */
typedef union {
  struct {
    UINT32 xpdfxsparereg_en_convert_invcmpl_urcmpl : 1;
    /* xpdfxsparereg_en_convert_invcmpl_urcmpl - Bits[0:0], RW_LV, default = 1'b0 
       if set to '1' will convert CMPLT_INV to CMPLT_MA inbound
     */
    UINT32 xpdfxsparereg_dis_perfboost_pktgen : 1;
    /* xpdfxsparereg_dis_perfboost_pktgen - Bits[1:1], RW_LV, default = 1'b1 
       if reset to '0' increase the perf b.w to 10.6GB/s from 8.0GB/s
     */
    UINT32 rsvd_2 : 3;
    /* rsvd_2 - Bits[4:2], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 en_ib_poison_ma : 1;
    /* en_ib_poison_ma - Bits[5:5], RW_LV, default = 1'b0 
       Set MA hint on all inbound packets with EP=1. Useful for containment of inbound 
       poison writes that trigger LER. 
     */
    UINT32 ler_epnp_dis : 1;
    /* ler_epnp_dis - Bits[6:6], RW_LV, default = 1'b0 
       Disable enhanced fix for LER containment and credit returns (ignored if 
       ler_ob_contain==0). 
     */
    UINT32 ler_ob_contain : 1;
    /* ler_ob_contain - Bits[7:7], RW_LV, default = 1'b1 
       Enable LER containment of subsequent packets from the LER triggering packet.
     */
    UINT32 xpdfxsparereg_bits0 : 8;
    /* xpdfxsparereg_bits0 - Bits[15:8], RW_LV, default = 8'b00000000  */
    UINT32 xpdfxsparereg_disloweraddr : 1;
    /* xpdfxsparereg_disloweraddr - Bits[16:16], RW_LV, default = 1'b0  */
    UINT32 xpdfxsparereg_discmpl_lowaddr : 1;
    /* xpdfxsparereg_discmpl_lowaddr - Bits[17:17], RW_LV, default = 1'b1  */
    UINT32 disable_msi_gt_1dw : 1;
    /* disable_msi_gt_1dw - Bits[18:18], RW_LV, default = 1'b0 
       If set to 1, Requests with address GT 51 bits and MSI GT 1 DW will not be logged 
       by the PCIE Transaction Layer. 
     */
    UINT32 xpdfxsparereg_en_ecn271_uncerr : 1;
    /* xpdfxsparereg_en_ecn271_uncerr - Bits[19:19], RW_LV, default = 1'b0  */
    UINT32 xpdfxsparereg_en_gosmsg_and_rstwarn_during_abort_inbound : 1;
    /* xpdfxsparereg_en_gosmsg_and_rstwarn_during_abort_inbound - Bits[20:20], RW_LV, default = 1'b1  */
    UINT32 xpdfxsparereg_dis_atomic_poison_check : 1;
    /* xpdfxsparereg_dis_atomic_poison_check - Bits[21:21], RW_LV, default = 1'b0  */
    UINT32 xpdfxsparereg_dis_cfgwr_cmplt_check : 1;
    /* xpdfxsparereg_dis_cfgwr_cmplt_check - Bits[22:22], RW_LV, default = 1'b1  */
    UINT32 xpdfxsparereg_dis_incorrect_cmpl_returned : 1;
    /* xpdfxsparereg_dis_incorrect_cmpl_returned - Bits[23:23], RW_LV, default = 1'b1  */
    UINT32 xpdfxsparereg_dis_incorrect_addr5_2_check : 1;
    /* xpdfxsparereg_dis_incorrect_addr5_2_check - Bits[24:24], RW_LV, default = 1'b1  */
    UINT32 xpdfxsparereg_dis_incorrect_lk_cmpl_check : 1;
    /* xpdfxsparereg_dis_incorrect_lk_cmpl_check - Bits[25:25], RW_LV, default = 1'b1  */
    UINT32 xpdfxsparereg_dis_len_1_0_check : 1;
    /* xpdfxsparereg_dis_len_1_0_check - Bits[26:26], RW_LV, default = 1'b1 
       if set to '0' will compare the LEN[1:0] of the received CMPL dev[4:3] with 
       LEN[1:0] 
     */
    UINT32 xpdfxsparereg_en_x16_ler_check : 1;
    /* xpdfxsparereg_en_x16_ler_check - Bits[27:27], RW_LV, default = 1'b0  */
    UINT32 xpdfxsparereg_en_x16_ler_dump : 1;
    /* xpdfxsparereg_en_x16_ler_dump - Bits[28:28], RW_LV, default = 1'b0  */
    UINT32 rsvd_29 : 1;
    /* rsvd_29 - Bits[29:29], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 enable_at_switch_swizzle : 1;
    /* enable_at_switch_swizzle - Bits[30:30], RW_LV, default = 1'b1 
       If set to 1, the AT field in the switch header will be zero for ACS completer 
       abort cases. 
     */
    UINT32 enable_acs_mem_check : 1;
    /* enable_acs_mem_check - Bits[31:31], RW_LV, default = 1'b1 
       If set to 1, Memory Requests with AT=11 and Memory Writes with AT=01 will be 
       logged by the PCIE Transaction Layer. 
     */
  } Bits;
  UINT32 Data;
} XPDFXSPAREREG_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* XPDFXSPAREREG1_IIO_DFX_IOSF_REG supported on:                              */
/*       BDX (0x40033B44)                                                     */
/* Register default value:              0x00000000                            */
#define XPDFXSPAREREG1_IIO_DFX_IOSF_REG 0x12034B44

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.IOSF.xml.
 * generated by critter 06_3_0xb44
 */
typedef union {
  struct {
    UINT32 rsvd_0 : 1;
    /* rsvd_0 - Bits[0:0], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 xpdfxsparereg1_dis_fifo_overrun_fix : 1;
    /* xpdfxsparereg1_dis_fifo_overrun_fix - Bits[1:1], RW_L, default = 1'b0 
       Disable 4620918 fix for inbound fifo overrun
       Locked by SPARELCK
     */
    UINT32 rsvd_2 : 30;
    /* rsvd_2 - Bits[31:2], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} XPDFXSPAREREG1_IIO_DFX_IOSF_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


#endif /* IIO_DFX_IOSF_h */
